A direct memory access (DMA) controller implements data transfer requests to transfer data from one system address location to another system address location. For example, based on a transfer request the DMA controller can transfer data between a memory of an integrated circuit and an external memory. Some types of memory, such as double data rate (DDR) memory can queue multiple data read requests from one or more communication channels, and can re-order the data read requests so that data for a later received access request is accessed by the DDR memory prior to data for an earlier received access request.
For example, a DDR can re-order data read requests to facilitate the occurrence of page hitting requests, and delay the occurrence of page colliding read requests. A page hitting data request is a data access request that has a target address with a bank and page that is the same as the bank and page of the DDR memory that is already open. A page colliding data transfer request is a data access request that has a target address with the same bank but different page as that already open at the DDR memory.
When the DDR memory receives a page hitting data access request, the DDR memory can perform the request and return a read response based on the data access request without having to close or open any pages in the DDR memory. However, when the DDR memory receives a page colliding data access request, the DDR memory first closes the currently opened page and then opens a new page targeted by the data access request. Thus, a DDR memory's read response for page colliding data access requests is slower than its read response for page hitting data access requests. To avoid this delay a DDR memory can execute a later received read request before an earlier received read request if it is to an open page of the DDR memory. However, for in-order communication channels, e.g., data channels that need to return information in the order requested, this re-ordering can cause a channel to become blocked, as returning read access request data out of order can result in information being received not being sent to the requesting device. Thus, blocking the channel until the first requested data is received.